library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity MIOMUX_logic is
    port(MIO_EN: in bit;
         LogicLDMDR_out,Mem_out: in unsigned(15 downto 0);
         MDR_in: out unsigned(15 downto 0));
     end entity MIOMUX_logic;
     
architecture build of MIOMUX_logic is
    begin
        process(LogicLDMDR_out,Mem_out,MIO_EN)
            begin
                if MIO_EN = '0' then
                    MDR_in <= LogicLDMDR_out;
                elsif MIO_EN = '1' then
                    MDR_in <= Mem_out;
                end if;
         end process;
    end build;
